Minimig_wb (WishBone)

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This project would involve porting Minimig to a larger FPGA platform, such as my Avnet Xilinx® Spartan®-3 Evaluation Kit using a XC3S1500 FPGA (it seems another project already is doing exactly this), particularly as a testing platform for my Zorro to Wishbone bridge project. I'll be very excited to see more about the AGA update to Minimig, and base my Wishbone project on that rather than the current ECS version of Minimig. There apparently was an old and apparently dead project to update to AGA here, the REAL project by yaqube I'm waiting to see a repository address for, but a lot of discussion about it is on amiga.org.

Minimig is essentially an SoC (System on Chip) product, with a limited feature set. I'd like to see IDE hard drives, ethernet, Zorro bus, PCI bus, and a wider variety of things added to Minimig, and I think that Wishbone is the easiest path to such additions. There are already a variety of such peripherals on Opencores.org in Wishbone bus format with open-source licensing compatible with the GPL Minimig. Although, some of these IPs are licensed as BSD, no license listed, etc. so I need to find out if they are license-compatible with Minimig's GPL before distributing anything.

I have worked on ARM based SoC chips at work, in a few contexts, but am still more of a junior engineer at the front-end side of things (Verilog RTL coding, simulation) than I am at back-end stuff (I did a lot of custom layout, place/route etc. in the past) Something fun to experiment with and gain experience from, in the little free time that I wish I had.

Note that most everything I list here is in the Verilog language.While the Altera De1/DE2 port of Minimig using the TG68 cpu core show that Verilog and VHDL can be mixed, I do not know of any free/open-source simulators that run on both at the same time. Icarus, Verilator and gpl-cver are all Verilog-only, GHDL is VHDL-only, etc. NC, Modelsim and other commercial simulators can do mixed-language, but I'd like to try to use free/open tools, not commercial tools even if they have no-cost versions capable of this. (I don't know that the free/no-cost Xilinx/Altera FPGA editions of these tools have mixed-language capability or not) And I'm somewhat comfortable with Verilog, though I probably know VHDL better at this point. Until free tools do mixed-language sims, I'll likely be as Verilog-only as I can be, just for simplicity, convenience, and Minimig is Verilog, and to gain experience there.

Here are some examples of items I'd like to see in Minimig_wb

Name	Language	Wishbone bus?	WB width Data/Addr	Description	License
minimig_aga	Verilog	no		Minimig design with AGA graphics. Not yet released. I assume it will be same location as the original Minimig source code. (will this be 16 or 32bit data bus?)	GPL 3
minimig	Verilog	no		Current Minimig design with older ECS graphics. 16bit data bus. MikeJ from FpgaArcade is porting Minimig to VHDL, though I haven't heard that bitstream or sources are released yet. Another project sounds like it has a port for my Avnet PCI card.	GPL 3
aoocs	Verilog	yes	32/30 (each addr is 4 bytes word size)	An independent OCS Amiga for FPGA design using Wishbone bus throughout.	BSD of some sort
Dragonball/68K Wishbone Interface	Verilog	yes	16/8 (each addr is 2 byte word size)	Bridge from 68K CPU bus to Wishbone bus. Hopefully this will be a quick and easy way to adapt the Minimig's 68K bus to the Wishbone bus. 16bit to 16bit data bus bridge.	Modified BSD/alike
ao68000	Verilog	yes	32/32	This is an implementation of the 68K CPU direct to a Wishbone bus, rather than the usual 68K bus. Seems like this and the Dragonball/68K Wishbone Interface are just waiting for me and Minimig! Is BSD license compatible with GPL Minimig? 32bit data and addr bus.	FreeBSD/alike
ae68	Verilog	yes		Another Wishbone bus 68000 processor. No files checked in yet. (07.Sept.2010) Project seems to have been disabled. (05.May.2011)	GPL
k68	Verilog	no	32/32	68000 processor, not Wishbone. Perhaps useful in testing the 68k/wishbone bridge before moving CPU to other side of it.	Modified BSD/alike
ocidec	Verilog & VHDL	yes	32/5	OpenCores IDE Controller for Wishbone bus. Verilog has rev 2, VHDL has rev 3.	Modified BSD/alike
Zorro to Wishbone Bridge	Verilog	yes	Z2=16/? Z3=32/? WB=32/32	My own project to create a verilog bridge between Wishbone and Amiga's Zorro2/3 bus. I'd like this to be as usable as possible, supporting 16 or 32bit data bus on Wishbone side, and all Zorro widths. (Zorro2 is 16bit, Zorro3 is 32bit). Would any 64bit WB side be reasonable too???	LGPL 2.1 or later
10M/100Mbit Ethernet MAC	Verilog	yes	32/10	Ethernet controller for 10/100Mbit speeds on Wishbone.	LGPL 2.1 or later
USB 2.0 controller	Verilog	yes	32/13 (addr is configurable)	USB2.0 controller for Wishbone.	Modified BSD/alike
DDR SDRAM controller	Verilog	yes	32/32	Memory controller for DDR SDRAM on Wishbone. Opencores page info broken, see bugtracker info here for the working repository. Ownersays get latest DDR design code from here. Opencores project is disabled. (05.May.2011)	LGPL on opencores page, (no version mentioned) but not mentioned in any files. Email response says GPL3, he may change to LGPL3 later.
FLASH memory controller	Verilog	yes	32/19	Memory controller for FLASH memory on Wishbone.	LGPL 2.1 or later
AC97 audio from Milkymist	Verilog			AC97 audio for Wishbone, from Milkymist project. Sure, we emulate Amiga's Paula, but what the heck? I'd love to see an HD Audio as well, but don't find a free/open one yet.	GPL 3
AC97	Verilog	yes	32/32	Another AC97 audio core for Wishbone.	Modified BSD/alike
Wishbone to AHB bus	Verilog	yes	32/16	AHB host/master bridge to attach Wishbone slave peripherals to. AHB is one of the busses used in ARM based Soc chips. Imagine Minimig/aoocs with an ARM processor?! Or adding AHB peripherals to Minimig... For those interested in ARM, there is a 68k emulation for ARM host called Cyclone 68000.	Modified BSD/alike (shown in doc file, not in source file)
Another AMBA/AHB bridge	Verilog	yes	32/32	AHB host/master bridge to attach a Wishbone slave peripheral to.	LGPL from project main page, not in source files, does not give version of LGPL
A third AHB bridge!	Verilog	yes	32/32	Wishbone host bridge to attach AHB peripherals to. (I think)	Modified BSD/alike (shown in doc file, not in source file)
Memory Controller	Verilog			Does SDRAM, FLASH, others on Wishbone.	Modified BSD/alike
SCSI	Verilog			Not Wishbone, but could be adapted somewhere. Project is no longer suspended it seems. Only code is in web_uploads, not trunk.To bad, would be cool for an Amiga FPGA project.	Doesn't say
HD-Audio controller	VHDL	no		First open-source HD-Audio (Azalia) controller I've found.	MIT License
zCore PPC	?	?	?	PowerPC Compatible CPU core. Just added to OpenCores, doesn't say much of anything yet, and no files checked in yet. They say it's FPGA proven though. This won't immediately make Minimig an OS4 machine, but it sounds interesting to have a look at.	GPL
LCD Graphics	VHDL			Graphical LCD panel control for KS0108b controllers	Doesn't say, will try to contact author. (never got a response)
IEEE 1394 (aka Firewire)	Verilog			OK, Amiga doesn't have a Firewire software stack. If it had hardware, there'd be more reason for the software. Well, I guess that PCI slots and PCI Firewire cards haven't lead to the software stack yet, but I do believe that in the argument over the chicken or the egg coming first, it makes more sense to start with providing the hardware. Hard to test/debug the software if there's no hardware there... Alas, this looks like only a testbench code available, not a core. :(	Doesn't say